Ankieta: Jaki system operacyjnym preferujesz

SP6VGX · 06-07-2016 13:31

(06-07-2016 12:46)SP5FCS napisał(a): Pisząc pierwszy program w środowisku które posiada kreator projektu nie musimy nic wiedzieć o zegarze (ustawiony domyślnie) a tym bardziej o SysTicku i przerwaniach.

I wlasnie to nie jest najlepsze podejscie - bo tak na prawde jestesmy potem zwiazani z srodowiskiem jakie uzywamy. Tutaj mozna sie zwiazac z komercyjnymi rozwiazaniami lub cala masa darmowych, ale czasem drastycznie sie rozniacych.

Przeniesienie projektu z innego srodowiska rosnie do problemu zdobycia mount everest itd.

Zreszta u gory wkleilem jak wyglada projekt z kreatora w Eclipse + troche pluginow... ktore tez trzeba wybrac i doinstalowac po zainstalowaniu Eclipse CDT.

No chyba ze wtybieramy srodowisko pod Win i rezygnujemy z uzytkownikow na innych platformach.

Natomiast bez pojecia jak dany interfejs jest taktowany to nic sie nie zrobi... bo w tym przykladzie nawet ja nie wiem jak co jest taktowane z defaultu (bo po prostu nie pamietam tego) Smile

Natomiast jak dla mnie sprawa wyjasnienia podstawy takiej jak ustawienie procesora dla danego kwarcu jaki mamy na plytce to jest niezbedna podstawa by cokolwiek pisac wiecej niz miganie dioda...

I tutaj znowu ile poczatkujacych wyedytuje ten plik i ustawi choc by poprawne wartosci dla wybranej plytki discovery ?

Kod:

/**

  *********************************************​*********************************

  * @file    system_stm32f4xx.c

  * @author  MCD Application Team

  * @version V1.7.0

  * @date    22-April-2016

  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.

  *          This file contains the system clock configuration for STM32F4xx devices.

  *             

  * 1.  This file provides two functions and one global variable to be called from 

  *     user application:

  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier

  *                      and Divider factors, AHB/APBx prescalers and Flash settings),

  *                      depending on the configuration made in the clock xls tool. 

  *                      This function is called at startup just after reset and 

  *                      before branch to main program. This call is made inside

  *                      the "startup_stm32f4xx.s" file.

  *

  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used

  *                                  by the user application to setup the SysTick 

  *                                  timer or configure other parameters.

  *                                     

  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must

  *                                 be called whenever the core clock is changed

  *                                 during program execution.

  *

  * 2. After each device reset the HSI (16 MHz) is used as system clock source.

  *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to

  *    configure the system clock before to branch to main program.

  *

  * 3. If the system clock source selected by user fails to startup, the SystemInit()

  *    function will do nothing and HSI still used as system clock source. User can 

  *    add some code to deal with this issue inside the SetSysClock() function.

  *

  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define

  *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or

  *    through PLL, and you are using different crystal you have to adapt the HSE

  *    value to your own configuration.

  *

  * 5. This file configures the system clock as follows:

  *============================================​=================================

  *============================================​=================================

  *                    Supported STM32F40xxx/41xxx devices

  *-----------------------------------------------------------------------------

  *        System Clock source                    | PLL (HSE)

  *-----------------------------------------------------------------------------

  *        SYSCLK(Hz)                             | 168000000

  *-----------------------------------------------------------------------------

  *        HCLK(Hz)                               | 168000000

  *-----------------------------------------------------------------------------

  *        AHB Prescaler                          | 1

  *-----------------------------------------------------------------------------

  *        APB1 Prescaler                         | 4

  *-----------------------------------------------------------------------------

  *        APB2 Prescaler                         | 2

  *-----------------------------------------------------------------------------

  *        HSE Frequency(Hz)                      | 25000000

  *-----------------------------------------------------------------------------

  *        PLL_M                                  | 25

  *-----------------------------------------------------------------------------

  *        PLL_N                                  | 336

  *-----------------------------------------------------------------------------

  *        PLL_P                                  | 2

  *-----------------------------------------------------------------------------

  *        PLL_Q                                  | 7

  *-----------------------------------------------------------------------------

  *        PLLI2S_N                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_R                               | NA

  *-----------------------------------------------------------------------------

  *        I2S input clock                        | NA

  *-----------------------------------------------------------------------------

  *        VDD(V)                                 | 3.3

  *-----------------------------------------------------------------------------

  *        Main regulator output voltage          | Scale1 mode

  *-----------------------------------------------------------------------------

  *        Flash Latency(WS)                      | 5

  *-----------------------------------------------------------------------------

  *        Prefetch Buffer                        | ON

  *-----------------------------------------------------------------------------

  *        Instruction cache                      | ON

  *-----------------------------------------------------------------------------

  *        Data cache                             | ON

  *-----------------------------------------------------------------------------

  *        Require 48MHz for USB OTG FS,          | Disabled

  *        SDIO and RNG clock                     |

  *-----------------------------------------------------------------------------

  *============================================​=================================

  *============================================​=================================

  *                    Supported STM32F42xxx/43xxx devices

  *-----------------------------------------------------------------------------

  *        System Clock source                    | PLL (HSE)

  *-----------------------------------------------------------------------------

  *        SYSCLK(Hz)                             | 180000000

  *-----------------------------------------------------------------------------

  *        HCLK(Hz)                               | 180000000

  *-----------------------------------------------------------------------------

  *        AHB Prescaler                          | 1

  *-----------------------------------------------------------------------------

  *        APB1 Prescaler                         | 4

  *-----------------------------------------------------------------------------

  *        APB2 Prescaler                         | 2

  *-----------------------------------------------------------------------------

  *        HSE Frequency(Hz)                      | 25000000

  *-----------------------------------------------------------------------------

  *        PLL_M                                  | 25

  *-----------------------------------------------------------------------------

  *        PLL_N                                  | 360

  *-----------------------------------------------------------------------------

  *        PLL_P                                  | 2

  *-----------------------------------------------------------------------------

  *        PLL_Q                                  | 7

  *-----------------------------------------------------------------------------

  *        PLLI2S_N                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_R                               | NA

  *-----------------------------------------------------------------------------

  *        I2S input clock                        | NA

  *-----------------------------------------------------------------------------

  *        VDD(V)                                 | 3.3

  *-----------------------------------------------------------------------------

  *        Main regulator output voltage          | Scale1 mode

  *-----------------------------------------------------------------------------

  *        Flash Latency(WS)                      | 5

  *-----------------------------------------------------------------------------

  *        Prefetch Buffer                        | ON

  *-----------------------------------------------------------------------------

  *        Instruction cache                      | ON

  *-----------------------------------------------------------------------------

  *        Data cache                             | ON

  *-----------------------------------------------------------------------------

  *        Require 48MHz for USB OTG FS,          | Disabled

  *        SDIO and RNG clock                     |

  *-----------------------------------------------------------------------------

  *============================================​=================================

  *============================================​=================================

  *                         Supported STM32F401xx devices

  *-----------------------------------------------------------------------------

  *        System Clock source                    | PLL (HSE)

  *-----------------------------------------------------------------------------

  *        SYSCLK(Hz)                             | 84000000

  *-----------------------------------------------------------------------------

  *        HCLK(Hz)                               | 84000000

  *-----------------------------------------------------------------------------

  *        AHB Prescaler                          | 1

  *-----------------------------------------------------------------------------

  *        APB1 Prescaler                         | 2

  *-----------------------------------------------------------------------------

  *        APB2 Prescaler                         | 1

  *-----------------------------------------------------------------------------

  *        HSE Frequency(Hz)                      | 25000000

  *-----------------------------------------------------------------------------

  *        PLL_M                                  | 25

  *-----------------------------------------------------------------------------

  *        PLL_N                                  | 336

  *-----------------------------------------------------------------------------

  *        PLL_P                                  | 4

  *-----------------------------------------------------------------------------

  *        PLL_Q                                  | 7

  *-----------------------------------------------------------------------------

  *        PLLI2S_N                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_R                               | NA

  *-----------------------------------------------------------------------------

  *        I2S input clock                        | NA

  *-----------------------------------------------------------------------------

  *        VDD(V)                                 | 3.3

  *-----------------------------------------------------------------------------

  *        Main regulator output voltage          | Scale1 mode

  *-----------------------------------------------------------------------------

  *        Flash Latency(WS)                      | 2

  *-----------------------------------------------------------------------------

  *        Prefetch Buffer                        | ON

  *-----------------------------------------------------------------------------

  *        Instruction cache                      | ON

  *-----------------------------------------------------------------------------

  *        Data cache                             | ON

  *-----------------------------------------------------------------------------

  *        Require 48MHz for USB OTG FS,          | Disabled

  *        SDIO and RNG clock                     |

  *-----------------------------------------------------------------------------

  *============================================​=================================

  *============================================​=================================

  *                Supported STM32F411xx/STM32F410xx devices

  *-----------------------------------------------------------------------------

  *        System Clock source                    | PLL (HSI)

  *-----------------------------------------------------------------------------

  *        SYSCLK(Hz)                             | 100000000

  *-----------------------------------------------------------------------------

  *        HCLK(Hz)                               | 100000000

  *-----------------------------------------------------------------------------

  *        AHB Prescaler                          | 1

  *-----------------------------------------------------------------------------

  *        APB1 Prescaler                         | 2

  *-----------------------------------------------------------------------------

  *        APB2 Prescaler                         | 1

  *-----------------------------------------------------------------------------

  *        HSI Frequency(Hz)                      | 16000000

  *-----------------------------------------------------------------------------

  *        PLL_M                                  | 16

  *-----------------------------------------------------------------------------

  *        PLL_N                                  | 400

  *-----------------------------------------------------------------------------

  *        PLL_P                                  | 4

  *-----------------------------------------------------------------------------

  *        PLL_Q                                  | 7

  *-----------------------------------------------------------------------------

  *        PLLI2S_N                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_R                               | NA

  *-----------------------------------------------------------------------------

  *        I2S input clock                        | NA

  *-----------------------------------------------------------------------------

  *        VDD(V)                                 | 3.3

  *-----------------------------------------------------------------------------

  *        Main regulator output voltage          | Scale1 mode

  *-----------------------------------------------------------------------------

  *        Flash Latency(WS)                      | 3

  *-----------------------------------------------------------------------------

  *        Prefetch Buffer                        | ON

  *-----------------------------------------------------------------------------

  *        Instruction cache                      | ON

  *-----------------------------------------------------------------------------

  *        Data cache                             | ON

  *-----------------------------------------------------------------------------

  *        Require 48MHz for USB OTG FS,          | Disabled

  *        SDIO and RNG clock                     |

  *-----------------------------------------------------------------------------

  *============================================​=================================

  *============================================​=================================

  *                         Supported STM32F446xx devices

  *-----------------------------------------------------------------------------

  *        System Clock source                    | PLL (HSE)

  *-----------------------------------------------------------------------------

  *        SYSCLK(Hz)                             | 180000000

  *-----------------------------------------------------------------------------

  *        HCLK(Hz)                               | 180000000

  *-----------------------------------------------------------------------------

  *        AHB Prescaler                          | 1

  *-----------------------------------------------------------------------------

  *        APB1 Prescaler                         | 4

  *-----------------------------------------------------------------------------

  *        APB2 Prescaler                         | 2

  *-----------------------------------------------------------------------------

  *        HSE Frequency(Hz)                      | 8000000

  *-----------------------------------------------------------------------------

  *        PLL_M                                  | 8

  *-----------------------------------------------------------------------------

  *        PLL_N                                  | 360

  *-----------------------------------------------------------------------------

  *        PLL_P                                  | 2

  *-----------------------------------------------------------------------------

  *        PLL_Q                                  | 7

  *-----------------------------------------------------------------------------

  *        PLL_R                                  | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_M                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_N                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_P                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_Q                               | NA

  *-----------------------------------------------------------------------------

  *        PLLI2S_R                               | NA

  *-----------------------------------------------------------------------------

  *        I2S input clock                        | NA

  *-----------------------------------------------------------------------------

  *        VDD(V)                                 | 3.3

  *-----------------------------------------------------------------------------

  *        Main regulator output voltage          | Scale1 mode

  *-----------------------------------------------------------------------------

  *        Flash Latency(WS)                      | 5

  *-----------------------------------------------------------------------------

  *        Prefetch Buffer                        | ON

  *-----------------------------------------------------------------------------

  *        Instruction cache                      | ON

  *-----------------------------------------------------------------------------

  *        Data cache                             | ON

  *-----------------------------------------------------------------------------

  *        Require 48MHz for USB OTG FS,          | Disabled

  *        SDIO and RNG clock                     |

  *-----------------------------------------------------------------------------

  *============================================​=================================

  *********************************************​*********************************

  * @attention

  *

  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>

  *

  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");

  * You may not use this file except in compliance with the License.

  * You may obtain a copy of the License at:

  *

  *        http://www.st.com/software_license_agreement_liberty_v2

  *

  * Unless required by applicable law or agreed to in writing, software 

  * distributed under the License is distributed on an "AS IS" BASIS, 

  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

  * See the License for the specific language governing permissions and

  * limitations under the License.

  *

  *********************************************​*********************************

  */

/** @addtogroup CMSIS

  * @{

  */

/** @addtogroup stm32f4xx_system

  * @{

  */  

/** @addtogroup STM32F4xx_System_Private_Includes

  * @{

  */

#include "stm32f4xx.h"

/**

  * @}

  */

/** @addtogroup STM32F4xx_System_Private_TypesDefinitions

  * @{

  */

/**

  * @}

  */

/** @addtogroup STM32F4xx_System_Private_Defines

  * @{

  */

/************************* Miscellaneous Configuration ************************/

/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted

     on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory  */     

#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)

/* #define DATA_IN_ExtSRAM */

#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */

#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)

/* #define DATA_IN_ExtSDRAM */

#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ 

#if defined(STM32F410xx) || defined(STM32F411xE)

/*!< Uncomment the following line if you need to clock the STM32F410xx/STM32F411xE by HSE Bypass

     through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed

     and is fixed at 8 MHz. 

     Hardware configuration needed for Nucleo Board:

     ñ SB54, SB55 OFF

     ñ R35 removed

     ñ SB16, SB50 ON */

/* #define USE_HSE_BYPASS */

#if defined(USE_HSE_BYPASS)     

#define HSE_BYPASS_INPUT_FREQUENCY   8000000

#endif /* USE_HSE_BYPASS */    

#endif /* STM32F410xx || STM32F411xE */

/*!< Uncomment the following line if you need to relocate your vector Table in

     Internal SRAM. */

/* #define VECT_TAB_SRAM */

#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 

                                   This value must be a multiple of 0x200. */

/**************************************************​****************************/

/************************* PLL Parameters *************************************/

#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)

 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */

 #define PLL_M      25

#elif defined(STM32F412xG) || defined (STM32F446xx)

 #define PLL_M      8

#elif defined (STM32F410xx) || defined (STM32F411xE)

 #if defined(USE_HSE_BYPASS)

  #define PLL_M      8    

 #else /* !USE_HSE_BYPASS */

  #define PLL_M      16

 #endif /* USE_HSE_BYPASS */

#else

#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */  

/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */

#define PLL_Q      7

#if defined(STM32F446xx)

/* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock =  PLL_VCO / PLLR */

#define PLL_R      7

#elif defined(STM32F412xG)

#define PLL_R      2

#else

#endif /* STM32F446xx */ 

#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)

#define PLL_N      360

/* SYSCLK = PLL_VCO / PLL_P */

#define PLL_P      2

#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */

#if defined (STM32F40_41xxx)

#define PLL_N      336

/* SYSCLK = PLL_VCO / PLL_P */

#define PLL_P      2

#endif /* STM32F40_41xxx */

#if defined(STM32F401xx)

#define PLL_N      336

/* SYSCLK = PLL_VCO / PLL_P */

#define PLL_P      4

#endif /* STM32F401xx */

#if defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG)

#define PLL_N      400

/* SYSCLK = PLL_VCO / PLL_P */

#define PLL_P      4   

#endif /* STM32F410xx || STM32F411xE */

/**************************************************​****************************/

/**

  * @}

  */

/** @addtogroup STM32F4xx_System_Private_Macros

  * @{

  */

/**

  * @}

  */

/** @addtogroup STM32F4xx_System_Private_Variables

  * @{

  */

#if defined(STM32F40_41xxx)

  uint32_t SystemCoreClock = 168000000;

#endif /* STM32F40_41xxx */

#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)

  uint32_t SystemCoreClock = 180000000;

#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */

#if defined(STM32F401xx)

  uint32_t SystemCoreClock = 84000000;

#endif /* STM32F401xx */

#if defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG)

  uint32_t SystemCoreClock = 100000000;

#endif /* STM32F410xx || STM32F401xE || STM32F412xG */

__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

/**

  * @}

  */

/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes

  * @{

  */

static void SetSysClock(void);

#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)

static void SystemInit_ExtMemCtl(void); 

#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */

/**

  * @}

  */

/** @addtogroup STM32F4xx_System_Private_Functions

  * @{

  */

/**

  * @brief  Setup the microcontroller system

  *         Initialize the Embedded Flash Interface, the PLL and update the 

  *         SystemFrequency variable.

  * @param  None

  * @retval None

  */

void SystemInit(void)

{

  /* FPU settings ------------------------------------------------------------*/

  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */

  #endif

  /* Reset the RCC clock configuration to the default reset state ------------*/

  /* Set HSION bit */

  RCC->CR |= (uint32_t)0x00000001;

  /* Reset CFGR register */

  RCC->CFGR = 0x00000000;

  /* Reset HSEON, CSSON and PLLON bits */

  RCC->CR &= (uint32_t)0xFEF6FFFF;

  /* Reset PLLCFGR register */

  RCC->PLLCFGR = 0x24003010;

  /* Reset HSEBYP bit */

  RCC->CR &= (uint32_t)0xFFFBFFFF;

  /* Disable all interrupts */

  RCC->CIR = 0x00000000;

#if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)

  SystemInit_ExtMemCtl(); 

#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */

  /* Configure the System clock source, PLL Multiplier and Divider factors, 

     AHB/APBx prescalers and Flash settings ----------------------------------*/

  SetSysClock();

  /* Configure the Vector Table location add offset address ------------------*/

#ifdef VECT_TAB_SRAM

  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */

#else

  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */

#endif

}

/**

   * @brief  Update SystemCoreClock variable according to Clock Register Values.

  *         The SystemCoreClock variable contains the core clock (HCLK), it can

  *         be used by the user application to setup the SysTick timer or configure

  *         other parameters.

  *           

  * @note   Each time the core clock (HCLK) changes, this function must be called

  *         to update SystemCoreClock variable value. Otherwise, any configuration

  *         based on this variable will be incorrect.         

  *     

  * @note   - The system frequency computed by this function is not the real 

  *           frequency in the chip. It is calculated based on the predefined 

  *           constant and the selected clock source:

  *             

  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)

  *                                              

  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)

  *                          

  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 

  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.

  *         

  *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value

  *             16 MHz) but the real value may vary depending on the variations

  *             in voltage and temperature.   

  *    

  *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value

  *              25 MHz), user has to ensure that HSE_VALUE is same as the real

  *              frequency of the crystal used. Otherwise, this function may

  *              have wrong result.

  *                

  *         - The result of this function could be not correct when using fractional

  *           value for HSE crystal.

  *     

  * @param  None

  * @retval None

  */

void SystemCoreClockUpdate(void)

{

  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;

#if defined(STM32F412xG) || defined(STM32F446xx)  

  uint32_t pllr = 2;

#endif /* STM32F412xG || STM32F446xx */

  /* Get SYSCLK source -------------------------------------------------------*/

  tmp = RCC->CFGR & RCC_CFGR_SWS;

  switch (tmp)

  {

    case 0x00:  /* HSI used as system clock source */

      SystemCoreClock = HSI_VALUE;

      break;

    case 0x04:  /* HSE used as system clock source */

      SystemCoreClock = HSE_VALUE;

      break;

    case 0x08:  /* PLL P used as system clock source */

       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N

         SYSCLK = PLL_VCO / PLL_P

         */    

      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;

      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;

#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)

      if (pllsource != 0)

      {

        /* HSE used as PLL clock source */

        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

      }

      else

      {

        /* HSI used as PLL clock source */

        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

      }

#elif defined(STM32F410xx) || defined(STM32F411xE)

#if defined(USE_HSE_BYPASS)

      if (pllsource != 0)

      {

        /* HSE used as PLL clock source */

        pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

      }  

#else  

      if (pllsource == 0)

      {

        /* HSI used as PLL clock source */

        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

      }  

#endif /* USE_HSE_BYPASS */  

#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F412xG ||  STM32F446xx || STM32F469_479xx */  

      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;

      SystemCoreClock = pllvco/pllp;      

      break;

#if defined(STM32F412xG) || defined(STM32F446xx)      

      case 0x0C:  /* PLL R used as system clock source */

       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N

         SYSCLK = PLL_VCO / PLL_R

         */    

      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;

      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;

      if (pllsource != 0)

      {

        /* HSE used as PLL clock source */

        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

      }

      else

      {

        /* HSI used as PLL clock source */

        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      

      }

      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;

      SystemCoreClock = pllvco/pllr;      

      break;

#endif /* STM32F412xG || STM32F446xx */

    default:

      SystemCoreClock = HSI_VALUE;

      break;

  }

  /* Compute HCLK frequency --------------------------------------------------*/

  /* Get HCLK prescaler */

  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];

  /* HCLK frequency */

  SystemCoreClock >>= tmp;

}

/**

  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 

  *         AHB/APBx prescalers and Flash settings

  * @Note   This function should be called only once the RCC clock configuration  

  *         is reset to the default reset state (done in SystemInit() function).   

  * @param  None

  * @retval None

  */

static void SetSysClock(void)

{

#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F412xG) || defined(STM32F446xx)|| defined(STM32F469_479xx)

/**************************************************​****************************/

/*            PLL (clocked by HSE) used as System clock source                */

/**************************************************​****************************/

  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  /* Enable HSE */

  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;

  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }

  if (HSEStatus == (uint32_t)0x01)

  {

    /* Select regulator voltage output Scale 1 mode */

    RCC->APB1ENR |= RCC_APB1ENR_PWREN;

    PWR->CR |= PWR_CR_VOS;

    /* HCLK = SYSCLK / 1*/

    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) ||  defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)    

    /* PCLK2 = HCLK / 2*/

    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;

    /* PCLK1 = HCLK / 4*/

    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;

#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx  || STM32F412xG || STM32F446xx || STM32F469_479xx */

#if defined(STM32F401xx)

    /* PCLK2 = HCLK / 2*/

    RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

    /* PCLK1 = HCLK / 4*/

    RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

#endif /* STM32F401xx */

#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)    

    /* Configure the main PLL */

    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);

#endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */

#if  defined(STM32F412xG) || defined(STM32F446xx)

    /* Configure the main PLL */

    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);

#endif /* STM32F412xG || STM32F446xx */    

    /* Enable the main PLL */

    RCC->CR |= RCC_CR_PLLON;

    /* Wait till the main PLL is ready */

    while((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }

#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)

    /* Enable the Over-drive to extend the clock frequency to 180 Mhz */

    PWR->CR |= PWR_CR_ODEN;

    while((PWR->CSR & PWR_CSR_ODRDY) == 0)

    {

    }

    PWR->CR |= PWR_CR_ODSWEN;

    while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)

    {

    }      

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;

#endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */

#if defined(STM32F40_41xxx)  || defined(STM32F412xG)   

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;

#endif /* STM32F40_41xxx  || STM32F412xG */

#if defined(STM32F401xx)

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;

#endif /* STM32F401xx */

    /* Select the main PLL as system clock source */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

    RCC->CFGR |= RCC_CFGR_SW_PLL;

    /* Wait till the main PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);

    {

    }

  }

  else

  { /* If HSE fails to start-up, the application will have wrong clock

         configuration. User can add here some code to deal with this error */

  }

#elif defined(STM32F410xx) || defined(STM32F411xE)

#if defined(USE_HSE_BYPASS) 

/**************************************************​****************************/

/*            PLL (clocked by HSE) used as System clock source                */

/**************************************************​****************************/

  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  /* Enable HSE and HSE BYPASS */

  RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);

  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;

  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }

  if (HSEStatus == (uint32_t)0x01)

  {

    /* Select regulator voltage output Scale 1 mode */

    RCC->APB1ENR |= RCC_APB1ENR_PWREN;

    PWR->CR |= PWR_CR_VOS;

    /* HCLK = SYSCLK / 1*/

    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

    /* PCLK2 = HCLK / 2*/

    RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

    /* PCLK1 = HCLK / 4*/

    RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

    /* Configure the main PLL */

    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);

    /* Enable the main PLL */

    RCC->CR |= RCC_CR_PLLON;

    /* Wait till the main PLL is ready */

    while((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;

    /* Select the main PLL as system clock source */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

    RCC->CFGR |= RCC_CFGR_SW_PLL;

    /* Wait till the main PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);

    {

    }

  }

  else

  { /* If HSE fails to start-up, the application will have wrong clock

         configuration. User can add here some code to deal with this error */

  }

#else /* HSI will be used as PLL clock source */

  /* Select regulator voltage output Scale 1 mode */

  RCC->APB1ENR |= RCC_APB1ENR_PWREN;

  PWR->CR |= PWR_CR_VOS;

  /* HCLK = SYSCLK / 1*/

  RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

  /* PCLK2 = HCLK / 2*/

  RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

  /* PCLK1 = HCLK / 4*/

  RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

  /* Configure the main PLL */

  RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24); 

  /* Enable the main PLL */

  RCC->CR |= RCC_CR_PLLON;

  /* Wait till the main PLL is ready */

  while((RCC->CR & RCC_CR_PLLRDY) == 0)

  {

  }

  /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;

  /* Select the main PLL as system clock source */

  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

  RCC->CFGR |= RCC_CFGR_SW_PLL;

  /* Wait till the main PLL is used as system clock source */

  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);

  {

  }

#endif /* USE_HSE_BYPASS */  

#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */  

}

#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)

#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\

    defined(STM32F469xx) || defined(STM32F479xx)

/**

  * @brief  Setup the external memory controller.

  *         Called in startup_stm32f4xx.s before jump to main.

  *         This function configures the external memories (SRAM/SDRAM)

  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).

  * @param  None

  * @retval None

  */

void SystemInit_ExtMemCtl(void)

{

  __IO uint32_t tmp = 0x00;

  register uint32_t tmpreg = 0, timeout = 0xFFFF;

  register uint32_t index;

  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */

  RCC->AHB1ENR |= 0x000001F8;

  /* Delay after an RCC peripheral clock enabling */

  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);

  /* Connect PDx pins to FMC Alternate function */

  GPIOD->AFR[0]  = 0x00CCC0CC;

  GPIOD->AFR[1]  = 0xCCCCCCCC;

  /* Configure PDx pins in Alternate function mode */  

  GPIOD->MODER   = 0xAAAA0A8A;

  /* Configure PDx pins speed to 100 MHz */  

  GPIOD->OSPEEDR = 0xFFFF0FCF;

  /* Configure PDx pins Output type to push-pull */  

  GPIOD->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PDx pins */ 

  GPIOD->PUPDR   = 0x00000000;

  /* Connect PEx pins to FMC Alternate function */

  GPIOE->AFR[0]  = 0xC00CC0CC;

  GPIOE->AFR[1]  = 0xCCCCCCCC;

  /* Configure PEx pins in Alternate function mode */ 

  GPIOE->MODER   = 0xAAAA828A;

  /* Configure PEx pins speed to 100 MHz */ 

  GPIOE->OSPEEDR = 0xFFFFC3CF;

  /* Configure PEx pins Output type to push-pull */  

  GPIOE->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PEx pins */ 

  GPIOE->PUPDR   = 0x00000000;

  /* Connect PFx pins to FMC Alternate function */

  GPIOF->AFR[0]  = 0xCCCCCCCC;

  GPIOF->AFR[1]  = 0xCCCCCCCC;

  /* Configure PFx pins in Alternate function mode */   

  GPIOF->MODER   = 0xAA800AAA;

  /* Configure PFx pins speed to 50 MHz */ 

  GPIOF->OSPEEDR = 0xAA800AAA;

  /* Configure PFx pins Output type to push-pull */  

  GPIOF->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PFx pins */ 

  GPIOF->PUPDR   = 0x00000000;

  /* Connect PGx pins to FMC Alternate function */

  GPIOG->AFR[0]  = 0xCCCCCCCC;

  GPIOG->AFR[1]  = 0xCCCCCCCC;

  /* Configure PGx pins in Alternate function mode */ 

  GPIOG->MODER   = 0xAAAAAAAA;

  /* Configure PGx pins speed to 50 MHz */ 

  GPIOG->OSPEEDR = 0xAAAAAAAA;

  /* Configure PGx pins Output type to push-pull */  

  GPIOG->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PGx pins */ 

  GPIOG->PUPDR   = 0x00000000;

  /* Connect PHx pins to FMC Alternate function */

  GPIOH->AFR[0]  = 0x00C0CC00;

  GPIOH->AFR[1]  = 0xCCCCCCCC;

  /* Configure PHx pins in Alternate function mode */ 

  GPIOH->MODER   = 0xAAAA08A0;

  /* Configure PHx pins speed to 50 MHz */ 

  GPIOH->OSPEEDR = 0xAAAA08A0;

  /* Configure PHx pins Output type to push-pull */  

  GPIOH->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PHx pins */ 

  GPIOH->PUPDR   = 0x00000000;

  /* Connect PIx pins to FMC Alternate function */

  GPIOI->AFR[0]  = 0xCCCCCCCC;

  GPIOI->AFR[1]  = 0x00000CC0;

  /* Configure PIx pins in Alternate function mode */ 

  GPIOI->MODER   = 0x0028AAAA;

  /* Configure PIx pins speed to 50 MHz */ 

  GPIOI->OSPEEDR = 0x0028AAAA;

  /* Configure PIx pins Output type to push-pull */  

  GPIOI->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PIx pins */ 

  GPIOI->PUPDR   = 0x00000000;

/*-- FMC Configuration -------------------------------------------------------*/

  /* Enable the FMC interface clock */

  RCC->AHB3ENR |= 0x00000001;

  /* Delay after an RCC peripheral clock enabling */

  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);

  FMC_Bank5_6->SDCR[0] = 0x000019E4;

  FMC_Bank5_6->SDTR[0] = 0x01115351;      

  /* SDRAM initialization sequence */

  /* Clock enable command */

  FMC_Bank5_6->SDCMR = 0x00000011; 

  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  while((tmpreg != 0) && (timeout-- > 0))

  {

    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  }

  /* Delay */

  for (index = 0; index<1000; index++);

  /* PALL command */

  FMC_Bank5_6->SDCMR = 0x00000012;           

  timeout = 0xFFFF;

  while((tmpreg != 0) && (timeout-- > 0))

  {

    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  }

  /* Auto refresh command */

  FMC_Bank5_6->SDCMR = 0x00000073;

  timeout = 0xFFFF;

  while((tmpreg != 0) && (timeout-- > 0))

  {

    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  }

  /* MRD register program */

  FMC_Bank5_6->SDCMR = 0x00046014;

  timeout = 0xFFFF;

  while((tmpreg != 0) && (timeout-- > 0))

  {

    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  } 

  /* Set refresh count */

  tmpreg = FMC_Bank5_6->SDRTR;

  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));

  /* Disable write protection */

  tmpreg = FMC_Bank5_6->SDCR[0]; 

  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);

#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)

  /* Configure and enable Bank1_SRAM2 */

  FMC_Bank1->BTCR[2]  = 0x00001011;

  FMC_Bank1->BTCR[3]  = 0x00000201;

  FMC_Bank1E->BWTR[2] = 0x0fffffff;

#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 

#if defined(STM32F469xx) || defined(STM32F479xx)

  /* Configure and enable Bank1_SRAM2 */

  FMC_Bank1->BTCR[2]  = 0x00001091;

  FMC_Bank1->BTCR[3]  = 0x00110212;

  FMC_Bank1E->BWTR[2] = 0x0fffffff;

#endif /* STM32F469xx || STM32F479xx */

  (void)(tmp); 

}

#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */

#elif defined (DATA_IN_ExtSRAM)

/**

  * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s 

  *          before jump to __main

  * @param  None

  * @retval None

  */ 

/**

  * @brief  Setup the external memory controller.

  *         Called in startup_stm32f4xx.s before jump to main.

  *         This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards

  *         This SRAM will be used as program data memory (including heap and stack).

  * @param  None

  * @retval None

  */

void SystemInit_ExtMemCtl(void)

{

/*-- GPIOs Configuration -----------------------------------------------------*/

/*

 +-------------------+--------------------+------------------+--------------+

 +                       SRAM pins assignment                               +

 +-------------------+--------------------+------------------+--------------+

 | PD0  <-> FMC_D2  | PE0  <-> FMC_NBL0 | PF0  <-> FMC_A0 | PG0 <-> FMC_A10 | 

 | PD1  <-> FMC_D3  | PE1  <-> FMC_NBL1 | PF1  <-> FMC_A1 | PG1 <-> FMC_A11 | 

 | PD4  <-> FMC_NOE | PE3  <-> FMC_A19  | PF2  <-> FMC_A2 | PG2 <-> FMC_A12 | 

 | PD5  <-> FMC_NWE | PE4  <-> FMC_A20  | PF3  <-> FMC_A3 | PG3 <-> FMC_A13 | 

 | PD8  <-> FMC_D13 | PE7  <-> FMC_D4   | PF4  <-> FMC_A4 | PG4 <-> FMC_A14 | 

 | PD9  <-> FMC_D14 | PE8  <-> FMC_D5   | PF5  <-> FMC_A5 | PG5 <-> FMC_A15 | 

 | PD10 <-> FMC_D15 | PE9  <-> FMC_D6   | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 | 

 | PD11 <-> FMC_A16 | PE10 <-> FMC_D7   | PF13 <-> FMC_A7 |-----------------+

 | PD12 <-> FMC_A17 | PE11 <-> FMC_D8   | PF14 <-> FMC_A8 | 

 | PD13 <-> FMC_A18 | PE12 <-> FMC_D9   | PF15 <-> FMC_A9 | 

 | PD14 <-> FMC_D0  | PE13 <-> FMC_D10  |-----------------+

 | PD15 <-> FMC_D1  | PE14 <-> FMC_D11  |

 |                  | PE15 <-> FMC_D12  |

 +------------------+------------------+

*/

   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */

  RCC->AHB1ENR   |= 0x00000078;

  /* Connect PDx pins to FMC Alternate function */

  GPIOD->AFR[0]  = 0x00cc00cc;

  GPIOD->AFR[1]  = 0xcccccccc;

  /* Configure PDx pins in Alternate function mode */  

  GPIOD->MODER   = 0xaaaa0a0a;

  /* Configure PDx pins speed to 100 MHz */  

  GPIOD->OSPEEDR = 0xffff0f0f;

  /* Configure PDx pins Output type to push-pull */  

  GPIOD->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PDx pins */ 

  GPIOD->PUPDR   = 0x00000000;

  /* Connect PEx pins to FMC Alternate function */

  GPIOE->AFR[0]  = 0xcccccccc;

  GPIOE->AFR[1]  = 0xcccccccc;

  /* Configure PEx pins in Alternate function mode */ 

  GPIOE->MODER   = 0xaaaaaaaa;

  /* Configure PEx pins speed to 100 MHz */ 

  GPIOE->OSPEEDR = 0xffffffff;

  /* Configure PEx pins Output type to push-pull */  

  GPIOE->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PEx pins */ 

  GPIOE->PUPDR   = 0x00000000;

  /* Connect PFx pins to FMC Alternate function */

  GPIOF->AFR[0]  = 0x00cccccc;

  GPIOF->AFR[1]  = 0xcccc0000;

  /* Configure PFx pins in Alternate function mode */   

  GPIOF->MODER   = 0xaa000aaa;

  /* Configure PFx pins speed to 100 MHz */ 

  GPIOF->OSPEEDR = 0xff000fff;

  /* Configure PFx pins Output type to push-pull */  

  GPIOF->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PFx pins */ 

  GPIOF->PUPDR   = 0x00000000;

  /* Connect PGx pins to FMC Alternate function */

  GPIOG->AFR[0]  = 0x00cccccc;

  GPIOG->AFR[1]  = 0x000000c0;

  /* Configure PGx pins in Alternate function mode */ 

  GPIOG->MODER   = 0x00080aaa;

  /* Configure PGx pins speed to 100 MHz */ 

  GPIOG->OSPEEDR = 0x000c0fff;

  /* Configure PGx pins Output type to push-pull */  

  GPIOG->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PGx pins */ 

  GPIOG->PUPDR   = 0x00000000;

/*-- FMC Configuration ------------------------------------------------------*/

  /* Enable the FMC/FSMC interface clock */

  RCC->AHB3ENR         |= 0x00000001;

#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)

  /* Configure and enable Bank1_SRAM2 */

  FMC_Bank1->BTCR[2]  = 0x00001011;

  FMC_Bank1->BTCR[3]  = 0x00000201;

  FMC_Bank1E->BWTR[2] = 0x0fffffff;

#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ 

#if defined(STM32F40_41xxx)

  /* Configure and enable Bank1_SRAM2 */

  FSMC_Bank1->BTCR[2]  = 0x00001011;

  FSMC_Bank1->BTCR[3]  = 0x00000201;

  FSMC_Bank1E->BWTR[2] = 0x0fffffff;

#endif  /* STM32F40_41xxx */

/*

  Bank1_SRAM2 is configured as follow:

  In case of FSMC configuration 

  NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;

  NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;

  NORSRAMTimingStructure.FSMC_DataSetupTime = 2;

  NORSRAMTimingStructure.FSMC_BusTurnAroundDura​tion = 0;

  NORSRAMTimingStructure.FSMC_CLKDivision = 0;

  NORSRAMTimingStructure.FSMC_DataLatency = 0;

  NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;

  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;

  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux​ = FSMC_DataAddressMux_Disable;

  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;

  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidt​h = FSMC_MemoryDataWidth_16b;

  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMod​e = FSMC_BurstAccessMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWa​it = FSMC_AsynchronousWait_Disable;  

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPola​rity = FSMC_WaitSignalPolarity_Low;

  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActi​ve = FSMC_WaitSignalActive_BeforeWaitState;

  FSMC_NORSRAMInitStructure.FSMC_WriteOperation​ = FSMC_WriteOperation_Enable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;

  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;

  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimin​gStruct = &NORSRAMTimingStructure;

  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStr​uct = &NORSRAMTimingStructure;

  In case of FMC configuration   

  NORSRAMTimingStructure.FMC_AddressSetupTime = 1;

  NORSRAMTimingStructure.FMC_AddressHoldTime = 0;

  NORSRAMTimingStructure.FMC_DataSetupTime = 2;

  NORSRAMTimingStructure.FMC_BusTurnAroundDurat​ion = 0;

  NORSRAMTimingStructure.FMC_CLKDivision = 0;

  NORSRAMTimingStructure.FMC_DataLatency = 0;

  NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;

  FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;

  FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;

  FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;

  FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;

  FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;

  FMC_NORSRAMInitStructure.FMC_AsynchronousWait​ = FMC_AsynchronousWait_Disable;  

  FMC_NORSRAMInitStructure.FMC_WaitSignalPolari​ty = FMC_WaitSignalPolarity_Low;

  FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;

  FMC_NORSRAMInitStructure.FMC_WaitSignalActive​ = FMC_WaitSignalActive_BeforeWaitState;

  FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;

  FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;

  FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;

  FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;

  FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;

  FMC_NORSRAMInitStructure.FMC_ReadWriteTimingS​truct = &NORSRAMTimingStructure;

  FMC_NORSRAMInitStructure.FMC_WriteTimingStruc​t = &NORSRAMTimingStructure;

*/

}  

#elif defined (DATA_IN_ExtSDRAM)

/**

  * @brief  Setup the external memory controller.

  *         Called in startup_stm32f4xx.s before jump to main.

  *         This function configures the external SDRAM mounted on STM324x9I_EVAL board

  *         This SDRAM will be used as program data memory (including heap and stack).

  * @param  None

  * @retval None

  */

void SystemInit_ExtMemCtl(void)

{

  register uint32_t tmpreg = 0, timeout = 0xFFFF;

  register uint32_t index;

  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 

      clock */

  RCC->AHB1ENR |= 0x000001FC;

  /* Connect PCx pins to FMC Alternate function */

  GPIOC->AFR[0]  = 0x0000000c;

  GPIOC->AFR[1]  = 0x00007700;

  /* Configure PCx pins in Alternate function mode */  

  GPIOC->MODER   = 0x00a00002;

  /* Configure PCx pins speed to 50 MHz */  

  GPIOC->OSPEEDR = 0x00a00002;

  /* Configure PCx pins Output type to push-pull */  

  GPIOC->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PCx pins */ 

  GPIOC->PUPDR   = 0x00500000;

  /* Connect PDx pins to FMC Alternate function */

  GPIOD->AFR[0]  = 0x000000CC;

  GPIOD->AFR[1]  = 0xCC000CCC;

  /* Configure PDx pins in Alternate function mode */  

  GPIOD->MODER   = 0xA02A000A;

  /* Configure PDx pins speed to 50 MHz */  

  GPIOD->OSPEEDR = 0xA02A000A;

  /* Configure PDx pins Output type to push-pull */  

  GPIOD->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PDx pins */ 

  GPIOD->PUPDR   = 0x00000000;

  /* Connect PEx pins to FMC Alternate function */

  GPIOE->AFR[0]  = 0xC00000CC;

  GPIOE->AFR[1]  = 0xCCCCCCCC;

  /* Configure PEx pins in Alternate function mode */ 

  GPIOE->MODER   = 0xAAAA800A;

  /* Configure PEx pins speed to 50 MHz */ 

  GPIOE->OSPEEDR = 0xAAAA800A;

  /* Configure PEx pins Output type to push-pull */  

  GPIOE->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PEx pins */ 

  GPIOE->PUPDR   = 0x00000000;

  /* Connect PFx pins to FMC Alternate function */

  GPIOF->AFR[0]  = 0xcccccccc;

  GPIOF->AFR[1]  = 0xcccccccc;

  /* Configure PFx pins in Alternate function mode */   

  GPIOF->MODER   = 0xAA800AAA;

  /* Configure PFx pins speed to 50 MHz */ 

  GPIOF->OSPEEDR = 0xAA800AAA;

  /* Configure PFx pins Output type to push-pull */  

  GPIOF->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PFx pins */ 

  GPIOF->PUPDR   = 0x00000000;

  /* Connect PGx pins to FMC Alternate function */

  GPIOG->AFR[0]  = 0xcccccccc;

  GPIOG->AFR[1]  = 0xcccccccc;

  /* Configure PGx pins in Alternate function mode */ 

  GPIOG->MODER   = 0xaaaaaaaa;

  /* Configure PGx pins speed to 50 MHz */ 

  GPIOG->OSPEEDR = 0xaaaaaaaa;

  /* Configure PGx pins Output type to push-pull */  

  GPIOG->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PGx pins */ 

  GPIOG->PUPDR   = 0x00000000;

  /* Connect PHx pins to FMC Alternate function */

  GPIOH->AFR[0]  = 0x00C0CC00;

  GPIOH->AFR[1]  = 0xCCCCCCCC;

  /* Configure PHx pins in Alternate function mode */ 

  GPIOH->MODER   = 0xAAAA08A0;

  /* Configure PHx pins speed to 50 MHz */ 

  GPIOH->OSPEEDR = 0xAAAA08A0;

  /* Configure PHx pins Output type to push-pull */  

  GPIOH->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PHx pins */ 

  GPIOH->PUPDR   = 0x00000000;

  /* Connect PIx pins to FMC Alternate function */

  GPIOI->AFR[0]  = 0xCCCCCCCC;

  GPIOI->AFR[1]  = 0x00000CC0;

  /* Configure PIx pins in Alternate function mode */ 

  GPIOI->MODER   = 0x0028AAAA;

  /* Configure PIx pins speed to 50 MHz */ 

  GPIOI->OSPEEDR = 0x0028AAAA;

  /* Configure PIx pins Output type to push-pull */  

  GPIOI->OTYPER  = 0x00000000;

  /* No pull-up, pull-down for PIx pins */ 

  GPIOI->PUPDR   = 0x00000000;

/*-- FMC Configuration ------------------------------------------------------*/

  /* Enable the FMC interface clock */

  RCC->AHB3ENR |= 0x00000001;

  /* Configure and enable SDRAM bank1 */

  FMC_Bank5_6->SDCR[0] = 0x000039D0;

  FMC_Bank5_6->SDTR[0] = 0x01115351;      

  /* SDRAM initialization sequence */

  /* Clock enable command */

  FMC_Bank5_6->SDCMR = 0x00000011; 

  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  while((tmpreg != 0) & (timeout-- > 0))

  {

    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  }

  /* Delay */

  for (index = 0; index<1000; index++);

  /* PALL command */

  FMC_Bank5_6->SDCMR = 0x00000012;           

  timeout = 0xFFFF;

  while((tmpreg != 0) & (timeout-- > 0))

  {

  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  }

  /* Auto refresh command */

  FMC_Bank5_6->SDCMR = 0x00000073;

  timeout = 0xFFFF;

  while((tmpreg != 0) & (timeout-- > 0))

  {

  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  }

  /* MRD register program */

  FMC_Bank5_6->SDCMR = 0x00046014;

  timeout = 0xFFFF;

  while((tmpreg != 0) & (timeout-- > 0))

  {

  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 

  } 

  /* Set refresh count */

  tmpreg = FMC_Bank5_6->SDRTR;

  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));

  /* Disable write protection */

  tmpreg = FMC_Bank5_6->SDCR[0]; 

  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);

/*

  Bank1_SDRAM is configured as follow:

  FMC_SDRAMTimingInitStructure.FMC_LoadToActive​Delay = 2;      

  FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefr​eshDelay = 6;  

  FMC_SDRAMTimingInitStructure.FMC_SelfRefreshT​ime = 4;        

  FMC_SDRAMTimingInitStructure.FMC_RowCycleDela​y = 6;         

  FMC_SDRAMTimingInitStructure.FMC_WriteRecover​yTime = 2;      

  FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;                

  FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;               

  FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;

  FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;

  FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;

  FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;

  FMC_SDRAMInitStructure.FMC_InternalBankNumber​ = FMC_InternalBank_Number_4;

  FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; 

  FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;

  FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;

  FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;

  FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;

  FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;

*/

}

#endif /* DATA_IN_ExtSDRAM && DATA_IN_ExtSRAM */

/**

  * @}

  */

/**

  * @}

  */

/**

  * @}

  */    

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Wiem ze kurs ma byc ciekawy ale bez pewnych podstaw to jak prowadzenie go bez wymagania znajomosci C...

Zwlaszcza ze nie sa to setki godzin... wystarczy wspomniec ze jest arkusz ktorym mozna to sobie policzyc i wszystko pieknie jest rozrysowane.
Wystarczy szybko tylko te bloki omowic:

QRP73 · 06-07-2016 13:37

Przeczytalem caly watek i powiem tak, duzo postow malo konkretow.
Mam DiscoverySTM32F429I, kwarc 8Mhz. Jak ustawic CoreClock za pomoca funkcji CMSIS na 168Mhz ?
Bede wdzieczny za kod z opisem co i dlaczego. Moze jakis autorski SysemInit().
Ogladam kod funkcji SystemInit i trudno sie w tym polapac.

SP6VGX · 06-07-2016 15:00

(06-07-2016 13:37)QRP73 napisał(a): Przeczytalem caly watek i powiem tak, duzo postow malo konkretow.
Mam DiscoverySTM32F429I, kwarc 8Mhz. Jak ustawic CoreClock za pomoca funkcji CMSIS na 168Mhz ?
Bede wdzieczny za kod z opisem co i dlaczego. Moze jakis autorski SysemInit().
Ogladam kod funkcji SystemInit i trudno sie w tym polapac.

No i wlasnie kolega Marek potwierdzil to o czym pisze... zaczyna sie problem bo brak wiadomosci o tym jak to poustawiac.

No i teraz w sumie pytanie czy lecimy z kodem - czy zrobic opis jak sie ustawia zegary ?

Natomiast co do migania LED-em to przykladowy kod z libopencm3. Jednak trudno to porownac - tutaj nie wymagane jest grzebanie w jakichkolwiek innych plkach do main.c wystarczy dolinkowac bibloteke... ale tego nie zrobi sie kreatorem...

Kod:

/*

 * This file is part of the libopencm3 project.

 *

 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>

 * Copyright (C) 2011 Damjan Marion <damjan.marion@gmail.com>

 * Copyright (C) 2011 Mark Panajotovic <marko@electrontube.org>

 * Copyright (C) 2015 Piotr Esden-Tempski <piotr@esden.net>

 *

 * This library is free software: you can redistribute it and/or modify

 * it under the terms of the GNU Lesser General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public License

 * along with this library.  If not, see <http://www.gnu.org/licenses/>.

 */

#include <libopencm3/stm32/rcc.h>

#include <libopencm3/stm32/gpio.h>

/* Set STM32 to 168 MHz. */

static void clock_setup(void)

{

    rcc_clock_setup_hse_3v3(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]);

    /* Enable GPIOG clock. */

    rcc_periph_clock_enable(RCC_GPIOG);

}

static void gpio_setup(void)

{

    /* Set GPIO13-14 (in GPIO port G) to 'output push-pull'. */

    gpio_mode_setup(GPIOG, GPIO_MODE_OUTPUT,

            GPIO_PUPD_NONE, GPIO13 | GPIO14);

}

int main(void)

{

    int i;

    clock_setup();

    gpio_setup();

    /* Set two LEDs for wigwag effect when toggling. */

    gpio_set(GPIOG, GPIO13);

    /* Blink the LEDs (PG13 and PG14) on the board. */

    while (1) {

        /* Toggle LEDs. */

        gpio_toggle(GPIOG, GPIO13 | GPIO14);

        for (i = 0; i < 6000000; i++) { /* Wait a bit. */

            __asm__("nop");

        }

    }

    return 0;

}

kolejny przyklad z biblioteki z uzyciem systick dla funkcji opoznienia:

Kod:

/*

 * This file is part of the libopencm3 project.

 *

 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>

 * Copyright (C) 2011 Damjan Marion <damjan.marion@gmail.com>

 * Copyright (C) 2011 Mark Panajotovic <marko@electrontube.org>

 * Copyright (C) 2013 Chuck McManis <cmcmanis@mcmanis.com>

 * Copyright (C) 2015 Piotr Esden-Tempski <piotr@esden.net>

 *

 * This library is free software: you can redistribute it and/or modify

 * it under the terms of the GNU Lesser General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public License

 * along with this library.  If not, see <http://www.gnu.org/licenses/>.

 */

/* This version derived from fancy blink */

#include <libopencm3/stm32/rcc.h>

#include <libopencm3/stm32/gpio.h>

#include <libopencm3/cm3/nvic.h>

#include <libopencm3/cm3/systick.h>

/* monotonically increasing number of milliseconds from reset

 * overflows every 49 days if you're wondering

 */

volatile uint32_t system_millis;

/* Called when systick fires */

void sys_tick_handler(void)

{

    system_millis++;

}

/* sleep for delay milliseconds */

static void msleep(uint32_t delay)

{

    uint32_t wake = system_millis + delay;

    while (wake > system_millis);

}

/*

 * systick_setup(void)

 *

 * This function sets up the 1khz "system tick" count. The SYSTICK counter is a

 * standard feature of the Cortex-M series.

 */

static void systick_setup(void)

{

    /* clock rate / 1000 to get 1mS interrupt rate */

    systick_set_reload(168000);

    systick_set_clocksource(STK_CSR_CLKSOURCE_AHB​);

    systick_counter_enable();

    /* this done last */

    systick_interrupt_enable();

}

/* Set STM32 system clock to 168 MHz. */

static void clock_setup(void)

{

    rcc_clock_setup_hse_3v3(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]);

    /* Enable GPIOG clock. */

    rcc_periph_clock_enable(RCC_GPIOG);

}

static void gpio_setup(void)

{

    /* Set GPIO13-14 (in GPIO port G) to 'output push-pull'. */

    gpio_mode_setup(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,

            GPIO13 | GPIO14);

}

int main(void)

{

    clock_setup();

    gpio_setup();

    systick_setup();

    /* Set two LEDs for wigwag effect when toggling. */

    gpio_set(GPIOG, GPIO13);

    /* Blink the LEDs (PG13 and PG14) on the board. */

    while (1) {

        gpio_toggle(GPIOG, GPIO13 | GPIO14);

        msleep(100);

    }

    return 0;

}

tylko nie wiem czy jest sens przeklejac kody ktore dostepne sa tutaj:
https://github.com/libopencm3/libopencm3...s/stm32/f4

i jeszcze jakis przyklad z aktualnych moich testow libopencm3... fragment obslugi UART pod ktory podpiety jest GPS...

Kod:

void GPS_HardwareInit(void)

{

    /**************************************************​******************************

     *  Enable Clock

     **************************************************​******************************/

    rcc_periph_clock_enable(RCC_GPIOC);

    rcc_periph_clock_enable(RCC_USART3);

    /**************************************************​******************************

     *  Configure GPIO

     **************************************************​******************************/

    /* PC10 - TX, PC11 - RX */

    gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO10 | GPIO11);

    /* PC12 - Reset */

    gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO12);

    /* PC11, PC12 - Out OpenDrain */

    gpio_set_output_options(GPIOC, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO11 | GPIO12);

    /* AF7 - USART3 */

    gpio_set_af(GPIOC, GPIO_AF7, GPIO10 | GPIO11);

    /* PC12 - Reset Off */

    gpio_set(GPIOC, GPIO12);

    /**************************************************​******************************

     *  Configure USART

     **************************************************​******************************/

    usart_set_baudrate(USART3, 9600);

    usart_set_databits(USART3, 8);

    usart_set_stopbits(USART3, USART_STOPBITS_1);

    usart_set_mode(USART3, USART_MODE_RX);

    usart_set_parity(USART3, USART_PARITY_NONE);

    usart_set_flow_control(USART3, USART_FLOWCONTROL_NONE);

    /**************************************************​******************************

     *  USART IRQ

     **************************************************​******************************/

    nvic_set_priority(NVIC_USART3_IRQ, 0);

    nvic_enable_irq(NVIC_USART3_IRQ);

    usart_enable_rx_interrupt(USART3);

    /**************************************************​******************************

     *  Enable USART

     **************************************************​******************************/

    usart_enable(USART3);

}

void usart3_isr(void)

{

    if (((USART_CR1(USART3) & USART_CR1_RXNEIE) != 0) && ((USART_SR(USART3) & USART_SR_RXNE) != 0))

    {

        GPS_ParseChar(usart_recv(USART3));

        if (GPSNmea.msg_available)

        {

            GPS_ParseNMEA();

            GPSNmea.msg_available = false;

        }

    }

}

SP5FCS · 07-07-2016 10:35

(06-07-2016 13:37)QRP73 napisał(a): Mam DiscoverySTM32F429I, kwarc 8Mhz. Jak ustawic CoreClock za pomoca funkcji CMSIS na 168Mhz ?

Zadanie Z001 "mruganie diodą"
W najprostszej wersji kodu do tego zadania wystarczy napisać funkcję programowego opóźnienia wait_ms i zmieniać w pętli stany na pinach diod umieszczonych na module disco. Do tego nie musimy mieć aktywnego SysTicka ani przerwań. Diody będą mrugały równo w rytmie pętli opóźnienia.
Gdyby jednak nasz program był bardziej rozbudowany i zawierał jakieś złożone zadania obsługiwane na przerwaniach to wtedy takt mrugania naszych diod będzie nierówny. Opóźnienie programowe będzie zależne od czasu obsługi przerwań.
Rozwiązanie mrugania diodą oparte na przerwaniu od SysTicka jest pozbawione tej wady, diody zawsze będą mrugały równo niezależnie od intensywności i czasu obsługi nawet wielu przerwań. Dlaczego ? Ponieważ ...

Jeśli ktoś ma ochotę pobawić się modułem Discovery_F429 oraz środowiskiem EMBitz to w załączniku jest paczka z projektem do pierwszego zadania. To jest kod Pawła z opisem jak przestawić zegar procesora na 168Mhz. Plik należy rozpakować do katalogu c:\F429\. Wszystkie niezbędne pliki będą w podkatalogu Z001. Poprawki na plikach są już zrobione. Diody mrugają co 500ms.
Debuger jest ustawiony pod J-link, proponuję podmienić oryginalne oprogramowanie ST-linka na Dicovery_F429 na obsługę J-linka.

Opis STLinkReflash

Ustawienie zegara procesora na module Discovery_F429
Zegar procesora STM32F429 zależy od częstotliwości rezonatora kwarcowego (pomijam generatory wewnętrzne) oraz współczynników pętli PLL:

SystemCoreClock = ((Xtal_Clock[HSE] / PLL_M) * PLL_N) / PLL_P

Przykładowe nastawy dla kwarcu 8Mhz:
STM32F429_180mhz, X=8mhz, HSE=8000000, PLL_M=8, PLL_N=360, PLL_P=2
STM32F429_168mhz, X=8mhz, HSE=8000000, PLL_M=8, PLL_N=336, PLL_P=2

STM32F429_168mhz=8000000/8*336/2=168000000Hz

Po wygenerowaniu nowego projektu pod STM32F429 w środowisku EMBitz w plikach startowych jest ustawione kwarc 25Mhz. Fizycznie na module Discovery_F429 mamy kwarc 8mhz dlatego musimy to zmieni. Powyższą "pułapkę" środowiska zlokalizował Paweł SQ8MVY podczas uruchamiania przykładowego kodu mrugania diodą.
Dla zegara 168Mhz musimy:
- 92 linia w pliku stm32f4xx.h - ustawi HSE=8000000 (domyslnie jest 25000000)
- 156 linia w pliku system_stm32f4xx.c - ustawic PLL_M=8 (domyslnie jest 25)

Aby wiedzieć z jaką szybkością są obsługiwane układy peryferyjne przyda się również informacja jak są ustawione dzielniki dla szyn procesora:
szyna AHB = SystemCoreClock / 1
szyna APB1 = SystemCoreClock / 4
szyna APB2 = SystemCoreClock / 2

Przy obsłudze USB musimy ustawić jeszcze dzielnik PLL_Q aby uzyskać 48Mhz.
Wszystkie współczynniki są zdefiniowane w pliku: system_stm32f4xx.c
Znajdziemy tam również tabelkę z domyślnymi nastawami procesara.

Tyle wiem na dziś, jak czegoś brakuje proszę o uzupełnienie.
Jeśli komuś te informacje nie wystarczą zachęcam do symulacji pod STM32Cube.

SP6VGX · 07-07-2016 11:41

Ja sie tylko tak zapytam, czyli mam nie robic opisu konfiguracji eclipse na kilka platform ? Bo widze ze na chwile obecna to nie ma sensu... korzystajac z kreatorow nie pogodzi sie tych srodowisk...

BTW ten problem z kwarcem to nie jest tylko problem EmBitz... w takiej formie sa przygotowane pliki CMSIS wiec czy dodamy z kreatora czy je sciagniemy w zip to tak beda ustawione. To nie jest pulapka tylko to o czym wspomnialem brak podstaw...

SP5FCS · 07-07-2016 11:49

Tomek, ależ rób jak najbardziej, wszyscy czekamy na jakieś konkretne opracowanie. Ja w tej chwili pracuję na tym co potrafię sam zainstalować i skonfigurować i tyle. Każde doświadczenie z procesorem się przyda niezależnie od tego na jakim środowisku będziemy ostatecznie pracowali.

Tomek, ciągle piszesz o braku podstaw. Większość z nas deklarowała się jako początkujący w temacie STM32 więc czego się spodziewałeś ?
Może czas opisywać te podstawy bo czas płynie, postów przybywa a wiedza na tym samym poziomie.

SP6VGX · 07-07-2016 13:37

Adam ok...

to w weekend przygotuje opis eclipse dla Win i OS X... jak ktos moze prosil bym o PW aby to zrobic z Linux-em (opis w zasadzie bedzie ten sam - roznica w sumie na poziomie podpieca gcc i instalacji softu jlinka, ewentualnie inne screenshoty).

Natomiast co do braku podstaw to wlasnie przy tworzeniu projektu wraz z opisem jak dodac go do srodowiska bez automatu - myslalem na szybko omowic kwestie zegarow na podstawie tego rysunku z exela. IMHO on o wiele bardziej przemawia do wyobrazni niz suchy wzorek...

QRP73 · 07-07-2016 17:54

Dla mnie wazne sa posty, ktore maja wartosc edukacyjna a tym w tym watku jest niewiele. Dyskusja jest wazna ale ja chcialbym sie czegos nauczyc aby samodzielnie pisac programy a nie tylko kompilowac dema. Dla mnie opis ustawienia zegara jest wystarczajacy bo ani kwarcu ani zegara nie musze zmieniac w kolejnych programach. W tym pierwszym przykladzie konfiguracja pinow jest bardzo uproszczona. Moze dadac pozostale parametry konfiguracji pinow. W SPLu robi sie to prosto ale na samym CMSIS bym tego nie umial zrobic. Pozostaje mi czekac na kolejne przyklady kodu.

SQ8MVY · 07-07-2016 21:38

Witaj,

Marku, dlaczego uważasz, że w przykładzie ustawienie pinów jest uproszczone ?
Pamiętaj, aby zapoznać się z dokumentem ReferenceManual STM32F4 , w którym opisane są peryferia. Nie trzeba czytać i przerabiać całego. Wystarczy zaglądnąć do konkretnego działu, a stanie się jasność.

Pytałeś się o zegary taktujące - informacje na ten temat znaleźć można w rozdziale 6.2

Należy pamiętać, że domyślnie wszystkie peryferia nie związane z rdzeniem są wyłączone i aby je użyć, należy najpierw włączyć im taktowanie.

Diody na naszej płytce Discovery są podłączone do portu GPIOG, do pinów 13 i 14

Kod:

RCC->AHB1ENR |= RCC_AHB1ENR_GPIOGEN;   // włączamy taktowanie portu GPIOG

Teraz zaglądniemy do rozdziału 6.3.10 i co widzimy ? Rejestr, za pomocą którego włączamy między innymi taktowanie portów. Jak widzisz, każdy port ma swój bit za to odpowiedzialny.

Kod:

GPIOG->MODER |=GPIO_MODER_MODER13_0 | GPIO_MODER_MODER14_0;  // ustawiamy pin 13 i 14 jako wyjście

W rozdziale 8 w/w dokumentu dowiedzieć się można w jakich trybach mogą pracować piny portów, na co wpływają bity konfiguracyjne rejestrów konfiguracyjnych portów. Idąc dalej dojdziemy do rozdziału 8.4, który teraz nas będzie interesował.
Rejestr GPIOx_MODER - ten ustawiamy powyższą linią kodu, a dokładnie bity MODER13 oraz MODER14 jako wyjścia.

Zostały jeszcze do ustawienia GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR. Zobaczmy najpierw jakie mają wartości domyślne i przeczytajmy to co jest pod tabelką każdego z tych rejestrów:

GPIOx_OTYPER - ustawiony jest domyślnie dla GPIOG jako output push-pull, czyli taki tryb nas interesuje, więc po co dodatkowo ustawiać to co jest ustawione ?

GPIOx_OSPEEDR - ustawiony jest domyślnie dla GPIOG jako low-speed - dla diodek nie trzeba nic przestawiać, bo chyba nie ma dla nich różnicy, czy zbocze będzie bardzo strome, czy będzie trochę pochylone. Świecić będą tak samo !!

GPIOx_PUPDR - tego rejestru też nie ma potrzeby ruszać bo i po co, skoro ustawienie w rejestrze GPIOx_OTYPER jest jako wyjście push-pull, więc dodawanie do tego dodatkowo rezystorów pull-up lub pull-down jest bezcelowe i nieekonomiczne

Kod:

GPIOG->ODR |= GPIO_ODR_ODR_13;  //ustawiamy na wyjściu 13 stan wysoki

GPIOx_ODR - rejestr wyjściowy portu. Ważne jest 16 młodszych bitów, które odpowiadają pinom 0..15 danego portu. Odczytując natomiast ten rejestr dostaniemy wartość, która została wpisana !!!

GPIOx_IDR - rejestr tylko do odczytu - odczytując go dostajemy informację o rzeczywistym stanie pinów, nawet jak pracują jako wyjściowe w trybie pull-up lub pull-down, open-drain (ale nie push-pull). Zwierając do masy (stan logiczny 0) lub do Vcc (stan logiczny 1) pin pracujący jako wyjście push-pull prawdopodobnie go uszkodzimy.

Jak więc widzisz, bez podstawowej znajomości dokumentacji i wiedzy jak się po niej poruszać ciężko jest zrozumieć, co jest ustawiane pisząc za pomocą bibliotek HAL, SPL, czy jeszcze innych, które się pojawią. A jak wiesz, w tych bibliotekach, czy jest potrzebne, czy nie i tak się wypełnia całą strukturę i przekazuje ją do funkcji bibliotecznej.

SP6VGX · 07-07-2016 22:38

Marek napisz moze jak bys widizal taki kurs z twojej perspektywy. Bo jak widac poszlo to z grubej rury i teraz tak czesc osob sie bedzie nudzic, a czesc nie bedzie wiedziec jak to dziala... Ja mam tam jakas koncepcje ale tez nie wiem czy bedzie dobra.

Generalnie na poczatku myslalem wlasnie aby opisac po kolei peryferia jak je sie konfiguruje + przyklad z opisem. W sumie zaczac od gpio po coraz trudniejesze do ustawienia.

Owszem co do zegarow wystarcay je raz skonfigurowac, ale np. wybierajac jakis timer musisz wiedziec z jakiej szyny i jaka czestotliwoscia on jest taktowany aby np. dobrac preskaler itp. i uzyskac np. wyzwalanie przerwania z okreslona czestotliwoscia. To samo tyczy sie szybkosci pracy innych blokow np. i2c itd.

Wszelkie uwagi innych poczatkujacych tez beda cenne.

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